Home page

EXPERIMENTAL HARDWARE PROJECT

QaviCoreX

An experimental RISC-V processor architecture exploring custom hardware acceleration for AI workloads.

Documentation

What is QaviCoreX?

QaviCoreX is an experimental processor project built around the RISC-V ecosystem. The project explores how a programmable RISC-V processor can be extended with specialized hardware operations designed around AI workloads.

The idea: Rather than treating AI acceleration as something completely separate from the processor, QaviCoreX explores bringing specialized AI-oriented operations closer to the processor architecture itself.

Technology Stack

RISC-V

The processor architecture is built around the open RISC-V instruction-set ecosystem.

Chisel

Hardware is described using Chisel, enabling parameterized hardware construction and integration with the RISC-V ecosystem.

FPGA

The design is being prototyped on FPGA hardware to evaluate the architecture in a real hardware environment.

AI Acceleration

The project investigates custom operations for AI-oriented computations.

AI-Oriented Instructions

One of the experimental directions of QaviCoreX is the addition of specialized instructions intended to accelerate common AI operations.

AIMAC

Experimental AI-oriented multiply-accumulate operation.

AIRELU

Experimental hardware operation targeting the ReLU activation function commonly used in neural networks.

AIMAX

Experimental operation targeting maximum-value selection, useful in AI processing pipelines.

These instructions are part of the experimental architecture and are being investigated through Chisel-based hardware implementation and FPGA prototyping.

Architecture

At a high level, the project explores the following path:

RISC-V Software ↓ RISC-V Instructions ↓ QaviCoreX Processor ↓ Custom AI Operations ↓ Hardware Execution ↓ FPGA Prototype

Project Status

✓ Architecture

The experimental processor architecture and integration work are under active development.

✓ Chisel Implementation

Hardware components and processor integration are being developed using Chisel.

✓ FPGA Prototyping

The design has progressed beyond a purely conceptual stage and is being evaluated through FPGA implementation.

⚠ Resource Scaling

The current FPGA prototype is approaching resource limits. LUT and other FPGA resource utilization are currently a major constraint for scaling the design.

Benchmarks

Benchmarking is an ongoing part of the project. The current focus is not only raw execution performance, but also determining how the architecture scales on real FPGA resources.

Current limitation: The available FPGA resources are becoming a bottleneck, particularly as the experimental processor and AI-oriented hardware are expanded.

A larger FPGA prototype is planned for future evaluation, which will allow the design to be tested at a larger scale and enable more meaningful performance measurements.

Why this project?

AI workloads increasingly rely on specialized computation. QaviCoreX explores a simple question:

What happens when AI-oriented operations become part of the processor architecture itself?

The project is an exploration of processor architecture, hardware acceleration, compiler/software integration, and FPGA implementation.

Open Development

QaviCoreX is being developed as an experimental and educational hardware project. The goal of this website is to document the architecture, implementation process, experiments, results, and lessons learned during development.

Selected source code, examples, documentation, simulations, and experiments can be made available through the project's public repository.

Explore QaviCoreX

Documentation

Architecture, setup instructions, design decisions, and implementation notes.

Source Code

Selected Chisel modules, integration code, examples, and supporting files.

Examples

Example programs demonstrating how the experimental architecture can be used.

Simulation

Simulation configurations and experiments used during development.

Benchmarks

Performance and resource measurements as the hardware implementation evolves.

Development Log

Follow the journey from architecture experiments to FPGA implementation.

QaviCoreX — Experimental RISC-V + AI Hardware

Built for research, experimentation and learning.