QaviCoreX Architecture

QaviCoreX is an experimental RISC-V processor architecture designed to explore specialized hardware acceleration for AI-oriented workloads.

High-Level Architecture

                ┌─────────────────────┐
                │    Software / OS    │
                └──────────┬──────────┘
                           │
                           ▼
                ┌─────────────────────┐
                │    RISC-V ISA       │
                └──────────┬──────────┘
                           │
                           ▼
                ┌─────────────────────┐
                │     QaviCoreX       │
                │    RISC-V Core      │
                └──────────┬──────────┘
                           │
             ┌─────────────┼─────────────┐
             │             │             │
             ▼             ▼             ▼
          AIMAC          AIRELU         AIMAX
             │             │             │
             └─────────────┼─────────────┘
                           │
                           ▼
                ┌─────────────────────┐
                │    FPGA Hardware    │
                └─────────────────────┘

Design Philosophy

The project investigates whether frequently used AI operations can be implemented closer to the processor execution path, reducing the need to express every operation purely through general-purpose instructions.

Implementation

The hardware is described using Chisel and integrated into the RISC-V/Chipyard ecosystem used during development.

Current Challenge

The major engineering challenge is scaling the design within the available FPGA resources. As additional hardware functionality is introduced, LUT and related resource utilization become increasingly important constraints.